What Does It Mean for an Input or an Output to Be Asserted
Chapter 4. Digital Logic
Embedded Systems - Shape The World
Jonathan Valvano and Ramesh Yerraballi
This chapter introduces digital logic. We will showtime ascertain what it means to be digital, and so introduce logic, voltages, gates, flip flops, registers, adders and memory. This affiliate is foundational, laying the ground work for the remainder of the class.
| Learning Objectives:
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Video 4.0. Digital Logic |
4.1. Binary Data Implemented with MOS transistors
Data is stored on the computer in binary form. A binary bit can exist in 1 of two possible states. In positive logic , the presence of a voltage is called the 'ane', truthful, asserted, or high land. The absence of a voltage is called the '0', false, not asserted, or low land. Figure 4.1 shows the output of a typical complementary metal oxide semiconductor (CMOS ) circuit. The left side shows the condition with a true flake, and the right side shows a faux. The output of each digital circuit consists of a p-type transistor "on peak of" an n-type transistor. In digital circuits, each transistor is substantially on or off. If the transistor is on, information technology is equivalent to a short excursion betwixt its two output pins. Conversely, if the transistor is off, it is equivalent to an open up circuit between its outputs pins.
Figure 4.1. A binary scrap is true if a voltage is present and simulated if the voltage is 0.
Every family unit of digital logic is a little different, only on a Stellaris ® microcontroller powered with 3.3 V supply, a voltage between 2 and 5 5 is considered loftier, and a voltage between 0 and 1.3 V is considered low, equally fatigued in Figure 4.2. Separating the two regions by 0.7 5 allows digital logic to operate reliably at very high speeds. The design of transistor-level digital circuits is beyond the scope of this class. However, it is important to know that digital data exist as binary bits and encoded as high and low voltages.
. What does binary mean?
Figure four.2. Mapping between analog voltage and the respective digital meaning on the TM4C123.
The maximum commanded voltage that the input will consider as low is called VIL . For the TM4C123, 5IL is 1.3V. The minimum allowable voltage that the input will consider as high is chosen VIH . For the TM4C123, VIH is 2.0V.
The output pin also has a range of normal operating voltages. When the output is low, the maximum possible voltage that an output can be is called VOL . For the TM4C123, VOL is 0.4V. This means the output of the TM4C123 volition be betwixt 0 and 0.4V when the microcontroller is sending a depression. When the output is loftier, the minimum possible voltage that an output can be is called VOH . For the TM4C123, VOH is 2.4V. This means the output of the TM4C123 will be between 2.4 and iii.3V when the microcontroller is sending a high. This information tin can be plant in Section 24.2 of TM4C123 data sheet.
If the information we wish to store exists in more than 2 states, we use multiple bits. A drove of two bits has 4 possible states (00, 01, 10, and 11). A drove of iii bits has eight possible states (000, 001, 010, 011, 100, 101, 110, and 111). In general, a drove of n $.25 has 2 north states. For example, a byte contains eight bits, and is built by grouping 8 binary bits into 1 object, equally shown in Figure 4.3. Some other proper noun for a drove of 8 bits is octet (octo is Latin and Greek pregnant viii.) Information tin can take many forms, e.grand., numbers, logical states, text, instructions, sounds, or images. What the bits mean depends on how the data is organized and more chiefly how it is used. This figure shows one byte in the state representing the binary number 01100111. Again, the output voltage three.3V means true or 1, and the output voltage of 0V means false or 0.
Figure iv.iii. A byte is comprised of viii bits, in this case representing the binary number 01100111.
What these 8 bits mean depends on how the computer software chooses to interpret them. Possibilities include just are non limited to an unsigned integer, a signed integer, a part of a machine code, and a graphic symbol.
. Assume the excursion in Figure 4.3 contains an unsigned integer. What is the smallest unsigned integer that can be represented? What is the largest unsigned integer that can exist represented?
. Presume the excursion in Figure 4.three contains a signed 2'due south complement integer. What is the smallest unsigned integer that can exist represented? What is the largest unsigned integer that can be represented?
. If the data stored in Figure 4.iii stand for characters, how many characters could it stand for?
In this section, we will give just a little taste of how the computer digital logic in the calculator works. Transistors made with metal oxide semiconductors are called MOS. In the digital world MOS transistors can be thought of every bit voltage controlled switches. Circuits made with both p-type and n-type MOS transistors are called complementary metal oxide semiconductors or CMOS. The 74HC04 is a high-speed CMOS Not gate , equally shown in Figure 4.iv.
Effigy iv.4. CMOS implementation of a NOT gate.
Video 4.0. Pattern of a NOT gate in digital logic
There are simply a few rules one needs to know for understanding how CMOS transistor-level circuits work. Each transistor acts similar a switch between its source and drain pins. In full general, current can flow from source to drain beyond an active p-type transistor , and no current will flow if the switch is open. From a first approximation, we tin can assume no current flows into or out of the gate. For a p-blazon transistor, the switch will be closed (transistor active) if its gate is depression. A p-type transistor will be off (its switch is open up) if its gate is high.
The gate on the n-type works in a complementary way, hence the name complementary metal oxide semiconductor. For an n-type transistor , the switch will be closed (transistor agile) if its gate is high. An n-type transistor volition exist off (its switch is open up) if its gate is depression. Therefore, consider the ii possibilities for the circuit in Effigy 4.four. If the input A is high (+3.3V), then the p-type transistor is off and the n-blazon transistor is active. The airtight switch beyond the source-drain of the n-blazon transistor volition brand the output low (0V). Conversely, if A is low (0V), then p-blazon transistor is active and the northward-type transistor is off. The closed switch across the source-bleed of the p-type transistor will brand the output high (+3.3V).
The AND, OR, EOR digital logic takes two inputs and produces 1 output; encounter Effigy four.five and Tabular array 4.ane. We can sympathize the operation of the AND gate past observing the behavior of its six transistors. If both inputs A and B are high, both T3 and T4 volition be active. Furthermore, if A and B are both loftier, T1 and T2 volition be off. In this case, the signal labeled ~(A&B) will be low because the T3–T4 switch combination volition brusk this signal to ground. If A is low, T1 will be active and T3 off. Similarly, if B is low, T2 will exist agile and T4 off. Therefore if either A is low or if B is low, the bespeak labeled ~(A&B) will exist high because i or both of the T1, T2 switches volition brusk this signal to +iii.3V. Transistors T5 and T6 create a logical complement, converting the betoken ~(A&B) into the desired issue of A&B. We tin use the and functioning to excerpt, or mask , individual bits from a value.
Effigy 4.five. Logical operations tin be implemented with discrete transistors or digital gates.
| A | B | AND | NAND | OR | NOR | EOR | Ex NOR |
| 0 | 0 | 0 | 1 | 0 | i | 0 | i |
| 0 | one | 0 | 1 | one | 0 | 1 | 0 |
| one | 0 | 0 | one | ane | 0 | i | 0 |
| 1 | ane | 1 | 0 | 1 | 0 | 0 | 1 |
| Symbol | A&B | ~(A&B) | A|B | ~(A|B) | A^B | ~(A^B) | |
Table iv.1. Two-input 1-output logical operations.
We can understand the operation of the OR gate past observing the behavior of its half-dozen transistors. If both inputs A and B are low, both T1 and T2 will be agile. Furthermore, if A and B are both low, T3 and T4 will exist off. In this instance, the point labeled ~(A|B) will be high considering the T1–T2 switch combination will short this signal to +3.3V. If A is high, T3 volition exist active and T1 off. Similarly, if B is high, T4 volition be active and T2 off. Therefore if either A is high or if B is high, the signal labeled ~(A|B) volition be low because ane or both of the T3, T4 switches will short this signal to ground. Transistors T5 and T6 create a logical complement, converting the betoken ~(A|B) into the desired result of A|B. We utilise the OR operation to set individual bits.
When writing software nosotros will have two kinds of logic operations. When operating on numbers (collection of bits) we volition perform logic operations flake by flake. In other words, the functioning is applied independently on each fleck. In C, the logic operator for AND is & . For example, if number A is 01100111 and number B is 11110000 then
A = 01100111
B = 11110000
A & B 01100000
The other type of logic functioning occurs when operating on Boolean values. In C, the status simulated is represented by the value 0, and truthful is any nonzero value. In this case, if the Boolean A is 01100111 and B is 11110000 then both A and B are true. The standard value for true is the value 1. In C, the Boolean operator for AND is && . Performing Boolean operation yields
A = 01100111
B = 11110000
A && B 1
In C, the logic operator for OR is | . The logic operation is applied independently on each bit . E.m.,
A = 01100111
B = 11110000
A | B 11110111
In C, the Boolean operator for OR is || . Performing Boolean operation of true OR truthful yields true. Although i is the standard value for a true, whatever nonzero value is considered as true.
A = 01100111
B = 11110000
A || B i
Other convenient logical operators are shown every bit digital gates in Figure 4.6. The NAND operation is defined by an AND followed by a Non. If you lot compare the transistor-level circuits in Figures 4.5 and 4.half-dozen, it would be more precise to say AND is defined as a NAND followed past a NOT. Similarly, the OR operation is a NOR followed past a NOT. The exclusive NOR operation implements the bit-wise equals operation.
Figure 4.6. Other logical operations can also be implemented with MOS transistors.
Video 4.1. Building a NAND gate
Boolean Algebra is the mathematical framework for digital logic. Some fundamental laws of Boolean Algebra are listed in Table four.2. With these laws, we consider A, B, C either as Booleans or as individual bits of a logic functioning.
| A & B = B & A | Commutative Law |
Table 4.2. Fundamental laws of Boolean Algebra.
. Let A bit an 8-scrap number, and consider the performance B=A&0x20, where A&0x20 is performed bit by bit. Now, if nosotros consider B as a Boolean value, what is the relationship between A and B?
. Permit C be an 8-chip number and consider the operation C=C&0xDF. How does this performance affect C?
. Permit D scrap an 8-bit number, and consider the operation D=D|0x20. How does this operation affect D?
When multiple operations occur in a single expression, precedence is used to determine the order of performance. Unremarkably Not is evaluated first, then AND, and then OR. This order can be altered using parentheses.
There are multiple means to symbolically represent the digital logic functions. For example, ~A A' 
. Let C bit an 8-fleck number. Are these two operations the same or different? C=C&0xDF C=C&(~0x20)
4.3. Flip-flops are used for storage
While we're introducing digital circuits, we need digital storage devices, which are essential components used to make registers and memory. The simplest storage device is the set-reset latch . I way to build a set-reset latch is shown on the left side of Figure 4.seven. If the inputs are S*=0 and R*=1, then the Q output volition exist 1. Conversely, if the inputs are Due south*=1 and R*=0, and so the Q output will exist 0. Ordinarily, nosotros leave both the S* and R* inputs high. We make the indicate South* go low, so dorsum loftier to set the latch, making Q=1. Conversely, we make the point R* go low, then back high to reset the latch, making Q=0. If both S* and R* are ane, the value on Q will be remembered or stored. This latch enters an unpredictable mode when S* and R* are simultaneously depression.
The gated D latch is also shown in Figure 4.7. The front end-end circuits take a data input, D, and a control point, W, and produce the South* and R* commands for the set-reset latch. For example, if West=0, then the latch is in its quiescent country, remembering the value on Q that was previously written. Nonetheless, if W=1, then the data input is stored into the latch. In particular, if D=1 and West=1, so Due south*=0 and R*=1, making Q=one. Furthermore, if D=0 and W=ane, and so S*=1 and R*=0, making Q=0. So, to use the gated latch, we offset put the information on the D input, next we brand W go high, and and then we make W go depression. This causes the data value to be stored at Q. Afterwards W goes depression, the data does not need to be at the D input anymore. If the D input changes while W is high, then the Q output volition alter correspondingly. Even so, the concluding value on the D input is remembered or latched when the W falls, every bit shown in Table 4.three.
The D flip-flop , shown on the right of Figure 4.seven, can also be used to store information. D flip-flops are the basic building cake of RAM and registers on the reckoner. To save information, nosotros offset place the digital value we wish to recollect on the D input, then requite a ascent edge to the clock input. After the rise edge of the clock, the value is available at the Q output, and the D input is free to modify. The operation of the clocked D flip-flop is defined on the correct side of Table iv.three. The 74HC374 is an viii-bit D flip-flop, such that all 8 $.25 are stored on the rise border of a single clock. The 74HC374 is like in structure and functioning to a register, which is loftier-speed memory inside the processor. If the gate (G) input on the 74HC374 is loftier, its outputs will exist HiZ (floating), and if the gate is low, the outputs will be loftier or depression depending on the stored values on the flip-flop. The D flip-flops are edge-triggered, meaning that changes in the output occur at the rise border of the input clock.
Effigy 4.vii. Digital storage elements.
| D | W | Q | D | clock | Q | |
| 0 | 0 | Qold | 0 | 0 | Qold | |
| 1 | 0 | Qold | 0 | 1 | Qold | |
| 0 | 1 | 0 | ane | 0 | Qold | |
| i | ane | 1 | 1 | 1 | Qerstwhile | |
| 0 | ↓ | 0 | 0 | ↑ | 0 | |
| ane | ↓ | 1 | 1 | ↑ | 1 |
Table 4.3. D flip-bomb operation. Qold is the value of the D input at the fourth dimension of fall of W or ascent of clock.
The tristate driver , shown in Figure 4.viii, can be used dynamically control signals inside the figurer. It is chosen tristate because at that place are three possible outputs: loftier, low, and HiZ. The tristate commuter is an essential component from which computers are built. To activate the commuter, we brand its gate (Yard*) low. When the driver is active, its output (Y) equals its input (A). To conciliate the driver, nosotros brand its M* high. When the driver is not agile, its output Y floats independent of A. Nosotros will also run across this floating state with the open collector logic, and information technology is likewise called HiZ or high impedance . The HiZ output means the output is neither driven high nor low. The performance of a tristate driver is defined in Tabular array 4.4. The 74HC244 is an viii-flake tristate driver, such that all 8 bits are active or non active controlled by a single gate. The 74HC374 8-bit D flip-bomb includes tristate drivers on its outputs. Normally, we tin't connect ii digital outputs together. The tristate driver provides a manner to connect multiple outputs to the same signal, as long as at most one of the gates is active at a time.
Figure 4.8. A 1-bit tristate driver and an viii-bit tristate driver (if Grand* is low, and then Y equals A, if Thou* is loftier, and so Y is HiZ). The indicate G* is negative logic.
Tabular array four.four describes how the tristate driver in Figure 4.8 works. Transistors T1 and T2 create the logical complement of Yard*. Similarly, transistors T3 and T4 create the complement of A. An input of G*=0 causes the driver to be active. In this example, both T5 and T8 will be on. With T5 and T8 on, the circuit behaves like a cascade of 2 Non gates, and so the output Y equals the input A. Nonetheless, if the input G*=1, both T5 and T8 volition be off. Since T5 is in series with the +three.3V, and T8 in series with the basis, the output Y will be neither high nor depression. I.e., it volition float.
| A | G* | T1 | T2 | T3 | T4 | T5 | T6 | T7 | T8 | Y |
| 0 | 0 | on | off | on | off | on | off | on | on | 0 |
| 1 | 0 | on | off | off | on | on | on | off | on | ane |
| 0 | 1 | off | on | on | off | off | off | on | off | HiZ |
| i | i | off | on | off | on | off | on | off | off | HiZ |
Table 4.four. Tristate commuter operation. HiZ is the floating state, such that the output is non high or low.
The output of an open up collector gate, drawn with the '×', has two states low (0V) and HiZ (floating) every bit shown in Figure 4.ix. Consider the operation of the transistor-level circuit for the 74HC05. If A is high (+3.3V), the transistor is active, and the output is depression (0V). If A is low (0V), the transistor is off, and the output is neither high nor depression. In general, we tin employ an open collector NOT gate to switch current on and off to a device, such as a relay, an LED, a solenoid, or a small motor. The 74HC05, the 74LS05, the 7405, and the 7406 are all open collector Non gates. 74HC04 is high-speed CMOS and can only sink up to 4 mA when its output is low. Since the 7405 and 7406 are transistor-transistor-logic (TTL) they tin can sink more current. In item, the 7405 has a maximum output low current (IOL ) of 16 mA, whereas the 7406 has a maximum IOL of 40 mA.
Figure 4.9. Two transistor implementations of an open collector NOT gate.
4.four. Binary Adder
The computer performs many arithmetic and logic operations. We will show one of them to illustrate some of the computation possible in the computer. We begin the design of an adder circuit with a simple subcircuit called a binary total adder , as shown in Figure 4.10. At that place are two binary information inputs A, B, and a carry input, Cin . There is i data output, Sout , and one conduct output, Cout . As shown in Table 4.v, Cin , A, and B are three independent binary inputs each of which could be 0 or 1. These three inputs are added together (the sum could exist 0, 1, 2, or 3), and the effect is encoded in the ii-bit binary result with Cout equally the virtually significant bit and Sout as the least significant bit. Cout is truthful if the sum is 2 or 3, and Southout is true if the sum is i or three.
Effigy 4.10. A binary full adder.
| A | B | Cin | A+B+Cin | Cout | Sout |
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | one | 1 | 0 | 1 |
| 0 | ane | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 2 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | ane | ii | 1 | 0 |
| 1 | 1 | 0 | 2 | 1 | 0 |
| ane | 1 | 1 | iii | 1 | ane |
Table 4.five. Input/output response of a binary full adder.
Figure iv.eleven shows an 8-bit adder formed by cascading eight binary total adders. Similarly, we build a 32-bit adder by cascading 32 binary full adders together. The bear into the 32-bit adder is zilch, and the carry out will be saved in the carry bit.
Figure 4.eleven. Nosotros make an 8-flake adder cascading eight binary full adders.
For an 8-fleck unsigned number, in that location are only 256 possible values, which are 0 to 255. When we add two 8-bit numbers the sum tin can be any number from 0 to 510, which is a 9-bit number. The 9-bit result in Figure 4.11 exists as the 8 bits R7–R0 plus carry.
We can call back of eight-fleck unsigned numbers as positions along a circle, like a clock. In that location is a discontinuity in the clock at the 0|255 interface; everywhere else adjacent numbers differ past ±1. If we add ii unsigned numbers, we get-go at the position of the first number a move in a clockwise direction the number of steps equal to the second number. If 96+64 is performed in eight-bit unsigned precision, the correct upshot of 160 is obtained. In this instance, the bear bit will be 0 signifying the answer is correct. On the other hand, if 224+64 is performed in 8-chip unsigned precision, the incorrect result of 32 is obtained. In this case, the carry chip will be 1, signifying the reply is wrong.
. If A has the value 100 (0x64) and B has the value 50 (0x32), what volition exist the value of the output (R7-R0) of the circuit in Effigy 4.eleven? Too what will the acquit indicate be?
. If A has the value 255 (0xFF) and B has the value two (0x02), what volition be the value of the output (R7-R0) of the circuit in Figure 4.11? Besides what will the carry signal be?
Memory is a collection of hardware elements in a computer into which we shop information, as shown in Figure iv.12. For nearly computers in today's market, each retentiveness cell contains ane byte of information, and each byte has a unique and sequential address. The memory is called byte-addressable because each byte has a separate address. The address of a retentiveness prison cell specifies its physical location, and its content is the data. When we write to retentiveness, nosotros specify an address and viii, 16, or 32 $.25 of information, causing that data to be stored into the memory. Typically information flows from processor into memory during a write cycle. When nosotros read from memory nosotros specify an address, causing 8, 16, or 32 $.25 of information to be retrieved from the retention. Typically data flows from memory into the processor during a read wheel. Read Only Retentivity, or ROM, is a type of memory where the data is programmed or burned into the device, and during normal operation it only allows read accesses. Random Access Memory (RAM) is used to shop temporary information, and during normal operation nosotros tin can read from or write data into RAM. The information in the ROM is nonvolatile , significant the contents are non lost when ability is removed. In dissimilarity, the information in the RAM is volatile , meaning the contents are lost when ability is removed. The organisation can quickly and conveniently read data from a ROM. It takes a comparatively long time to program or burn data into a ROM. Writing to Wink ROM is a two-step procedure. Offset, the ROM is erased, causing all the bits to become ane. 2nd, the system writes zeroes into the ROM as needed. Each of these ii steps requires effectually 1 ms to consummate. In contrast, it is fast and like shooting fish in a barrel to both read data from and write data into a RAM. Writing to RAM is nearly 100,000 times faster (on the social club of 10 ns). ROM on the other hand is much denser than RAM. This ways we can pack more than ROM bits into a fleck than we can pack RAM $.25. Most microcontrollers have much more ROM than RAM.
Figure 4.12. Retentiveness is a sequential drove of data storage elements.
In the computer, we can build an 8-fleck storage chemical element, shown logically as Effigy 4.12, by combining eight flip-flops. This basic storage element is called a register , as shown in Figure 4.13. A motorbus is a collection of wires used to pass information from one identify to another. In this circuit, the signals D7–D0 represent the data bus. Registers on the Stellaris ® microcontrollers are 32-bits wide, only in this example nosotros evidence an 8-fleck register. We call it storage considering as long the circuit remains powered, the digital information represented by the 8 voltages Q7–Q0 will be remembered. There are two operations one performs on a register: write and read . To perform a write, 1 first puts the desired information on the 8 data bus wires (D7–D0). Equally yous can encounter from Effigy 4.13, these data motorbus signals are present on the D inputs of the 8 flip-flops. Next, the system pulses the Write bespeak high then low. This Write pulse will latch or shop the desired data into the eight flip-flops. The read operation will place a copy of the register information onto the data bus. Notice the gate signals of the tristate drivers are negative logic. This means if the Read* signal is loftier, the tristate drivers are off, and this register does not affect signals on the autobus. However, the read operation occurs by setting the Read* indicate depression, which will place the register data onto the omnibus.
. What does negative logic mean?
Figure 4.xiii. Digital logic implementation of a register .
A not bad deal of confusion exists over the abbreviations nosotros use for large numbers. In 1998 the International Electrotechnical Commission (IEC) defined a new set of abbreviations for the powers of two, as shown in Table four.half-dozen. These new terms are endorsed by the Institute of Electrical and Electronics Engineers (IEEE ) and International Commission for Weights and Measures (CIPM) in situations where the utilise of a binary prefix is appropriate. The confusion arises over the fact that the mainstream computer industry, such every bit Microsoft, Apple, and Dell, continues to use the old terminology. According to the companies that market place to consumers, a 1 GHz is i,000,000,000 Hz but one Gbyte of memory is 1,073,741,824 bytes. The correct terminology is to use the SI-decimal abbreviations to represent powers of x, and the IEC-binary abbreviations to represent powers of two. The scientific meaning of 2 kilovolts is 2000 volts, but 2 kibibytes is the proper manner to specify 2048 bytes. The term kibibyte is a contraction of kilo binary byte and is a unit of information or computer storage, abbreviated KiB .
i KiB = 210 bytes = 1024 bytes
1 MiB = 220 bytes = 1,048,576 bytes
1 GiB = iithirty bytes = i,073,741,824 bytes
These abbreviations tin can also be used to specify the number of binary bits. The term kibibit is a wrinkle of kilo binary bit, and is a unit of data or computer storage, abbreviated Kibit .
A mebibyte (one MiB is 1,048,576 bytes) is approximately equal to a megabyte (1 MB is 1,000,000 bytes), just mistaking the two has even so led to confusion and fifty-fifty legal disputes. In the engineering science community, it is advisable to utilise terms that have a clear and unambiguous meaning.
| Value | SI Decimal | SI Decimal | Value | IEC Binary | IEC Binary | |
| grandi | k | kilo- | 10241 | Ki | kibi- | |
| mtwo | M | mega- | 10242 | Mi | mebi- | |
| one thousand3 | G | giga- | 10243 | Gi | gibi- | |
| 10004 | T | tera- | 10244 | Ti | tebi- | |
| 1000five | P | peta- | 10245 | Pi | pebi- | |
| chiliad6 | Due east | exa- | 10246 | Ei | exbi- | |
| 10007 | Z | zetta- | 1024vii | Zi | zebi- | |
| thousandeight | Y | yotta- | 10248 | Yi | yobi- |
Table 4.half dozen. Common abbreviations for large numbers.
4.1 Which of the post-obit is true. Positive logic is defined as
a) The configuration where the "true" state has a higher voltage than the "simulated" state.
b) The state where the signal is "high".
c) The state where the transistor is "on".
d) The country where the transistor is "off".
e) None of the above
4. two If a voltage on an input of the TM4C123 is between 0 and ane.3 V, how is that input considered?
a) Low or logic "0"
b) Unknown or illegal
c) High or logic "1"
4.3 If a voltage on an input of the TM4C123 is betwixt ane.three and ii 5, how is that input considered?
a) Depression or logic "0"
b) Unknown or illegal
c) High or logic "i"
iv.four If a voltage on an input of the TM4C123 is between ii and 5 V, how is that input considered?
a) Low or logic "0"
b) Unknown or illegal
c) High or logic "one"
4. five Calculate the logic expression for each set of inputs A, B, C
| A | B | C | A & (B | C) |
| 01002 = iv | 01012 = 5 | 01102 = 6 | |
| 01112 = 7 | 1010ii = 10 | 00012 = i | |
| 11102 = fourteen | 10012 = 9 | 01112 = 7 |
4.half-dozen Calculate the Boolean expression for each gear up of inputs A, B, C
| A | B | C | A && (B || C) |
| Truthful | Faux | Faux | |
| Truthful | False | True | |
| Fake | Truthful | False | |
| True | True | False |
Reprinted with blessing from Embedded Systems: Introduction to ARM Cortex-Chiliad Microcontrollers, 2014, ISBN: 978-1477508992, http://users.ece.utexas.edu/~valvano/arm/outline1.htm
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Source: http://users.ece.utexas.edu/~valvano/Volume1/E-Book/C4_DigitalLogic.htm
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